Synchronous semiconductor devices input and output data in synchronization with a clock signal. Such synchronous semiconductor devices may include a clock signal generator which generates an internal clock signal that is synchronized with an external clock signal.
When a semiconductor device inputs and outputs 4 bits or symbols of data per data input/output terminal during a single clock cycle, the semiconductor device includes a quadrature-phase signal generator which generates a quadrature-phase (i.e., multiphase) clock signal having a 90-degree phase difference from an external clock signal. Two or more multiphase signals may be needed. Multiphase signals may provide a high-speed interface to a semiconductor integrated circuit device so long as an unacceptable level of skew does not exist between the multiphase signals.
FIGS. 1 and 2 illustrate multiphase signals having no skew and multiphase signals having some skew, respectively. Referring to FIG. 1, second, third, and fourth clock signals CK1, CK2, and CK3 have exactly 90-degree, 180-degree and 270-degree phase differences, respectively, from a first clock signal CK0. Accordingly, there is no skew among the multiphase signals CK0 through CK3. In this case, 4-bit data D<3:0> can be input or output per clock cycle T and the four bits have the same timing, that is, the period of each bit is T/4. In contrast, referring to FIG. 2, the second, third, and fourth clock signals CK1, CK2, and CK3 do not have exactly 90-degree, 180-degree and 270-degree phase differences, respectively, from the first clock signal CK0. Accordingly, the periods of individual bits in the 4-bit data D<3:0>, which are input/output during a single clock cycle, are different from one another. In other words, the period of one or more bits may be longer than T/4 and the period of other bit(s) may be shorter than T/4.
The phase skew between multiphase signals may generate jitter in the output data and reduce the timing margin of a period in which the bit may be accurately sampled. As a result, it may be difficult to input/output data at high speed. In other words, the phase skew may hinder high-speed operation.